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clean up FPU code with some ideas from Chromium and the web
This commit is contained in:
Paul Davis
parent
3a1a978541
commit
41ccfee7a4
2 changed files with 176 additions and 132 deletions
301
libs/pbd/fpu.cc
301
libs/pbd/fpu.cc
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@ -29,6 +29,7 @@
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#include <intrin.h>
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#endif
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#include "pbd/compose.h"
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#include "pbd/fpu.h"
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#include "pbd/error.h"
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@ -37,178 +38,216 @@
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using namespace PBD;
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using namespace std;
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FPU::FPU ()
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{
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unsigned long cpuflags = 0;
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FPU* FPU::_instance (0);
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_flags = Flags (0);
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#ifndef COMPILER_MSVC
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/* use __cpuid() as the name to match the MSVC intrinsic */
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static void
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__cpuid(int regs[4], int cpuid_leaf)
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{
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int eax, ebx, ecx, edx;
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asm volatile (
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#if defined(__i386__)
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"pushl %%ebx;\n\t"
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#endif
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"movl %4, %%eax;\n\t"
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"cpuid;\n\t"
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"movl %%eax, %0;\n\t"
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"movl %%ebx, %1;\n\t"
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"movl %%ecx, %2;\n\t"
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"movl %%edx, %3;\n\t"
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#if defined(__i386__)
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"popl %%ebx;\n\t"
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#endif
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:"=m" (eax), "=m" (ebx), "=m" (ecx), "=m" (edx)
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:"r" (cpuid_leaf)
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:"%eax",
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#if !defined(__i386__)
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"%ebx",
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#endif
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"%ecx", "%edx");
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regs[0] = eax;
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regs[1] = ebx;
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regs[2] = ecx;
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regs[3] = edx;
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}
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static uint64_t
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_xgetbv (uint32_t xcr)
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{
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uint32_t eax, edx;
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__asm__ volatile ("xgetbv" : "=a" (eax), "=d" (edx) : "c" (xcr));
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return (static_cast<uint64_t>(edx) << 32) | eax;
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}
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#define _XCR_XFEATURE_ENABLED_MASK 0
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#endif /* !COMPILER_MSVC */
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FPU*
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FPU::instance()
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{
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if (!_instance) {
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_instance = new FPU;
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}
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return _instance;
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}
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FPU::FPU ()
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: _flags ((Flags) 0)
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{
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if (_instance) {
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error << _("FPU object instantiated more than once") << endmsg;
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}
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#if !( (defined __x86_64__) || (defined __i386__) || (defined _M_X64) || (defined _M_IX86) ) // !ARCH_X86
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/* Non-Intel architecture, nothing to do here */
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return;
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#else
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#ifdef PLATFORM_WINDOWS
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/* Get the CPU vendor just for kicks */
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// Get CPU flags using Microsoft function
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// It works for both 64 and 32 bit systems
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// no need to use assembler for getting info from register, this function does this for us
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int cpuInfo[4];
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__cpuid (cpuInfo, 1);
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cpuflags = cpuInfo[3];
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// __cpuid with an InfoType argument of 0 returns the number of
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// valid Ids in CPUInfo[0] and the CPU identification string in
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// the other three array elements. The CPU identification string is
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// not in linear order. The code below arranges the information
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// in a human readable form. The human readable order is CPUInfo[1] |
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// CPUInfo[3] | CPUInfo[2]. CPUInfo[2] and CPUInfo[3] are swapped
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// before using memcpy to copy these three array elements to cpu_string.
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#else
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int cpu_info[4];
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char cpu_string[48];
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string cpu_vendor;
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#ifndef _LP64 /* *nix; 32 bit version. This odd macro constant is required because we need something that identifies this as a 32 bit
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build on Linux and on OS X. Anything that serves this purpose will do, but this is the best thing we've identified
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so far.
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*/
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__cpuid (cpu_info, 0);
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int num_ids = cpu_info[0];
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std::swap(cpu_info[2], cpu_info[3]);
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memcpy(cpu_string, &cpu_info[1], 3 * sizeof(cpu_info[1]));
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cpu_vendor.assign(cpu_string, 3 * sizeof(cpu_info[1]));
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info << string_compose (_("CPU vendor: %1"), cpu_vendor) << endmsg;
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if (num_ids > 0) {
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asm volatile (
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"mov $1, %%eax\n"
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"pushl %%ebx\n"
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"cpuid\n"
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"movl %%edx, %0\n"
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"popl %%ebx\n"
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: "=r" (cpuflags)
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:
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: "%eax", "%ecx", "%edx"
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);
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/* Now get CPU/FPU flags */
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#else /* *nix; 64 bit version */
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/* asm notes: although we explicitly save&restore rbx, we must tell
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gcc that ebx,rbx is clobbered so that it doesn't try to use it as an intermediate
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register when storing rbx. gcc 4.3 didn't make this "mistake", but gcc 4.4
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does, at least on x86_64.
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*/
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__cpuid (cpu_info, 1);
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asm volatile (
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"pushq %%rbx\n"
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"movq $1, %%rax\n"
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"cpuid\n"
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"movq %%rdx, %0\n"
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"popq %%rbx\n"
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: "=r" (cpuflags)
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:
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: "%rax", "%rbx", "%rcx", "%rdx"
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);
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#endif /* _LP64 */
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#endif /* PLATFORM_WINDOWS */
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#ifndef __APPLE__
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/* must check for both AVX and OSXSAVE support in cpuflags before
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* attempting to use AVX related instructions.
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*/
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if ((cpuflags & (1<<27)) /* AVX */ && (cpuflags & (1<<28) /* (OS)XSAVE */)) {
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std::cerr << "Looks like AVX\n";
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/* now check if YMM resters state is saved: which means OS does
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* know about new YMM registers and saves them during context
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* switches it's true for most cases, but we must be sure
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*
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* giving 0 as the argument to _xgetbv() fetches the
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* XCR_XFEATURE_ENABLED_MASK, which we need to check for
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* the 2nd and 3rd bits, indicating correct register save/restore.
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*/
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uint64_t xcrFeatureMask = 0;
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#if __GNUC__ > 4 || __GNUC__ == 4 && __GNUC_MINOR__ >= 4
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unsigned int eax, edx, index = 0;
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asm volatile("xgetbv" : "=a"(eax), "=d"(edx) : "c"(index));
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xcrFeatureMask = ((unsigned long long)edx << 32) | eax;
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#elif defined (COMPILER_MSVC)
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xcrFeatureMask = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
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#endif
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if (xcrFeatureMask & 0x6) {
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std::cerr << "Definitely AVX\n";
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if ((cpu_info[2] & (1<<27)) /* AVX */ &&
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(cpu_info[2] & (1<<28) /* (OS)XSAVE */) &&
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(_xgetbv (_XCR_XFEATURE_ENABLED_MASK) & 0x6)) { /* OS really supports XSAVE */
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info << _("AVX-capable processor") << endmsg;
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_flags = Flags (_flags | (HasAVX) );
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}
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}
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#endif /* !__APPLE__ */
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if (cpuflags & (1<<25)) {
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_flags = Flags (_flags | (HasSSE|HasFlushToZero));
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}
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if (cpu_info[3] & (1<<25)) {
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_flags = Flags (_flags | (HasSSE|HasFlushToZero));
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}
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if (cpuflags & (1<<26)) {
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_flags = Flags (_flags | HasSSE2);
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}
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if (cpu_info[3] & (1<<26)) {
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_flags = Flags (_flags | HasSSE2);
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}
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if (cpuflags & (1 << 24)) {
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/* Figure out CPU/FPU denormal handling capabilities */
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if (cpu_info[3] & (1 << 24)) {
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char** fxbuf = 0;
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char** fxbuf = 0;
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/* DAZ wasn't available in the first version of SSE. Since
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setting a reserved bit in MXCSR causes a general protection
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fault, we need to be able to check the availability of this
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feature without causing problems. To do this, one needs to
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set up a 512-byte area of memory to save the SSE state to,
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using fxsave, and then one needs to inspect bytes 28 through
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31 for the MXCSR_MASK value. If bit 6 is set, DAZ is
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supported, otherwise, it isn't.
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*/
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/* DAZ wasn't available in the first version of SSE. Since
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setting a reserved bit in MXCSR causes a general protection
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fault, we need to be able to check the availability of this
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feature without causing problems. To do this, one needs to
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set up a 512-byte area of memory to save the SSE state to,
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using fxsave, and then one needs to inspect bytes 28 through
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31 for the MXCSR_MASK value. If bit 6 is set, DAZ is
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supported, otherwise, it isn't.
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*/
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#ifndef HAVE_POSIX_MEMALIGN
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# ifdef PLATFORM_WINDOWS
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fxbuf = (char **) _aligned_malloc (sizeof (char *), 16);
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assert (fxbuf);
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*fxbuf = (char *) _aligned_malloc (512, 16);
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assert (*fxbuf);
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fxbuf = (char **) _aligned_malloc (sizeof (char *), 16);
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assert (fxbuf);
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*fxbuf = (char *) _aligned_malloc (512, 16);
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assert (*fxbuf);
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# else
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# warning using default malloc for aligned memory
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fxbuf = (char **) malloc (sizeof (char *));
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assert (fxbuf);
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*fxbuf = (char *) malloc (512);
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assert (*fxbuf);
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fxbuf = (char **) malloc (sizeof (char *));
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assert (fxbuf);
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*fxbuf = (char *) malloc (512);
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assert (*fxbuf);
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# endif
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#else
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(void) posix_memalign ((void **) &fxbuf, 16, sizeof (char *));
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assert (fxbuf);
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(void) posix_memalign ((void **) fxbuf, 16, 512);
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assert (*fxbuf);
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(void) posix_memalign ((void **) &fxbuf, 16, sizeof (char *));
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assert (fxbuf);
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(void) posix_memalign ((void **) fxbuf, 16, 512);
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assert (*fxbuf);
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#endif
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memset (*fxbuf, 0, 512);
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memset (*fxbuf, 0, 512);
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#ifdef COMPILER_MSVC
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char *buf = *fxbuf;
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__asm {
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mov eax, buf
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fxsave [eax]
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};
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char *buf = *fxbuf;
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__asm {
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mov eax, buf
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fxsave [eax]
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};
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#else
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asm volatile (
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"fxsave (%0)"
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:
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: "r" (*fxbuf)
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: "memory"
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);
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asm volatile (
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"fxsave (%0)"
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:
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: "r" (*fxbuf)
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: "memory"
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);
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#endif
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uint32_t mxcsr_mask = *((uint32_t*) &((*fxbuf)[28]));
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uint32_t mxcsr_mask = *((uint32_t*) &((*fxbuf)[28]));
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/* if the mask is zero, set its default value (from intel specs) */
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/* if the mask is zero, set its default value (from intel specs) */
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if (mxcsr_mask == 0) {
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mxcsr_mask = 0xffbf;
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}
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if (mxcsr_mask == 0) {
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mxcsr_mask = 0xffbf;
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}
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if (mxcsr_mask & (1<<6)) {
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_flags = Flags (_flags | HasDenormalsAreZero);
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}
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if (mxcsr_mask & (1<<6)) {
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_flags = Flags (_flags | HasDenormalsAreZero);
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}
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#if !defined HAVE_POSIX_MEMALIGN && defined PLATFORM_WINDOWS
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_aligned_free (*fxbuf);
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_aligned_free (fxbuf);
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_aligned_free (*fxbuf);
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_aligned_free (fxbuf);
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#else
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free (*fxbuf);
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free (fxbuf);
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free (*fxbuf);
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free (fxbuf);
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#endif
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}
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#endif
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/* finally get the CPU brand */
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__cpuid (cpu_info, 0x80000000);
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const int parameter_end = 0x80000004;
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string cpu_brand;
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if (cpu_info[0] >= parameter_end) {
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char* cpu_string_ptr = cpu_string;
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for (int parameter = 0x80000002; parameter <= parameter_end &&
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cpu_string_ptr < &cpu_string[sizeof(cpu_string)]; parameter++) {
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__cpuid(cpu_info, parameter);
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memcpy(cpu_string_ptr, cpu_info, sizeof(cpu_info));
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cpu_string_ptr += sizeof(cpu_info);
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}
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cpu_brand.assign(cpu_string, cpu_string_ptr - cpu_string);
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info << string_compose (_("CPU brand: %1"), cpu_brand) << endmsg;
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}
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}
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#endif
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}
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FPU::~FPU ()
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@ -35,9 +35,10 @@ class LIBPBD_API FPU {
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};
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public:
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FPU ();
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~FPU ();
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static FPU* instance();
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bool has_flush_to_zero () const { return _flags & HasFlushToZero; }
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bool has_denormals_are_zero () const { return _flags & HasDenormalsAreZero; }
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bool has_sse () const { return _flags & HasSSE; }
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@ -46,6 +47,10 @@ class LIBPBD_API FPU {
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private:
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Flags _flags;
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static FPU* _instance;
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FPU ();
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};
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}
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